The present invention relates to color CCD area imagers.
The preferable way to operate a color CCD area imager is with three serial output registers, each having its own on-chip sense amplifier.
The present invention teaches the desirability of implementing the three sense amplifiers as correlated clamp sample and hold (correlated double sampling) amplifiers.
The CCSH amplifier architecture is well known, but it has not been integrated on chip with a CCD area imager in the prior art. A CCSH amplifier can provide improved noise rejection. By optimizing the CCSH amplifier, the noise can be minimized. In particular, reset noise can be reduced by using the CCSH architecture. This means that the imager has greater dynamic range and improved low light performance.
In particular, the prior art has also not taught use of a CCSH amplifier combined with a dummy charge-sensing node which is formed in the same semiconductor device layer as the active charge-sensing node for the amplifier (i.e., having the same topology and doping profiles, although not necessarily of exactly the same horizontal dimensions); and this combination provides even further improvements in low noise performance.
However, the CCSH amplifier requires three separate clock phases to control it. Moreover, in most system architectures, the relative phasing of the three different color channels is also constrained.
Thus, a straightforward implementation of a color CCD imager with CCSH sense amplifiers would require at least nine clock lines, including numerous phasing constraints among the clock lines.
The present invention teaches that, in a color CCD imager with CCSH sense amplifiers for each color channel, the three control lines for the three sense amplifiers are all wired together, but not in parallel: for example, the first sense amplifier's reset clock line may be hard wired together with the clamp clock line of the second sense amplifier and with the sample and hold clock line of the third sense amplifier, and the clamp clock line of the first sense amplifier may be wired together with the sample and hold clock line of the second sense amplifier and the reset clock line of the third sense amplifier, etc.
Moreover, the three clock signals which are thus used to operate the three sense amplifiers thus turn out to be the same clock signals as are used to clock charge packets along the three serial registers. Thus no additional wiring is required to carry control signals, beyond that required for operation of the three serial registers anyway.
This arrangement advantageously provides a reduced number of clock lines for a color CCD imager. This leads to simplified constraints on drive electronics and also less required metal area in laying out a monolithic CCD imager which has three CCSH amplifiers integrated with a CCD array on a single chip.
According to the present invention there is provided: A CCD color imager comprising: an image sensing area; a storage area comprising a plurality of chains of CCD wells; a multiplexer connected to ends of said chains of wells in said storage area; first, second, and third serial registers connected to receive signals through said multiplexer from said chains of wells; first, second, and third sense amplifiers each connected to a corresponding one of said serial registers, each comprising first, second, and third control inputs, said first control input of said first amplifier controlling the same function in said first amplifier as said first control input of said second amplifier controls in said second amplifier, said first control input of said first amplifier being commonly connected with said second control input of said second amplifier and with said third control input of said third amplifier.